module ram (
  input wire i_en,
  input wire i_clk,
  input wire [63:0] i_addr,
  input wire [63:0] i_data,
  output wire [63:0] o_data
);

reg [63:0] mem [1023:0];

always @(posedge i_clk) begin
  if (i_en) begin
    mem[i_addr] <= i_data;
  end
end

assign o_data = mem[i_addr];

endmodule